What you'd actually do

Coordinate interactions with Quantum Qubit design and Measurement teams to define specifications, architecture, and micro-architecture for Analog IP blocks. Own and drive the development of analog IP, including microarchitecture, schematic entry, and verification of complex blocks to meet stringent power, performance, and timing goals.

Create test plans for verification and post-silicon validation and characterization. Design and validate analog blocks in simulation, both pre- and post-layout. Drive design reviews, status reports, and schedules to deliver against internal end-to-end milestone quality.

Coordinate the work of other Analog Designers and Verification teams, audit their output, and provide guidance and direction to deliver high-quality results.

Develop basic test benches and support verification, Design For Test (DFT), and post-silicon validation activities for the products in partnership with verification and product teams.

Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams.

Skills

Required

Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment OR equivalent experience
analog IP development
microarchitecture
schematic entry
verification
power, performance, and timing goals
test plans
post-silicon validation
characterization
simulation
design reviews
analog mixed-signal design
physical design
DFT

Nice to have

quantum hardware
error correction
cryo-electronics
SoC architecture
verification
physical design
Design For Test (DFT)
post-silicon validation

Overview

At Microsoft Quantum, we aim to empower science and scientists to solve the world's biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence, and quantum information technology. Our team is dedicated to developing the first scalable, fault-tolerant quantum computer and is leading progress in areas ranging from quantum hardware and error correction to comprehensive integration with Azure. Our full-stack strategy spans the physics of quantum devices through scalable readout and control infrastructures powered by cryo-electronics. We are entering a pivotal phase of accelerated growth in quantum computing, and this position presents a unique opportunity to contribute meaningfully to a transformative technology. For more information about our team, visit https://www.microsoft.com/en-us/quantum.

As a Principal Quantum Analog Design Lead in the Quantum 1st Party Hardware Application-Specific Integrated Circuit (ASIC) team, you will play a critical leadership role in advancing the development of the team's quantum Analog infrastructure. Your responsibilities will include defining System-on-a-Chip (SoC) and Intellectual Property (IP) microarchitecture specifications, and coordinating individuals, contingent staff, and external vendors to deliver a high-quality design.

You will work across SoC architecture, quantum hardware, verification, and physical design teams throughout the program lifecycle to bring SoC and IP into production at the quality required for scalable quantum systems. If you thrive on complex challenges and foundational technologies that redefine what's possible, we invite you to help shape the future of quantum computing.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Responsibilities

Coordinate interactions with Quantum Qubit design and Measurement teams to define specifications, architecture, and micro-architecture for Analog IP blocks. Own and drive the development of analog IP, including microarchitecture, schematic entry, and verification of complex blocks to meet stringent power, performance, and timing goals.
Create test plans for verification and post-silicon validation and characterization. Design and validate analog blocks in simulation, both pre- and post-layout. Drive design reviews, status reports, and schedules to deliver against internal end-to-end milestone quality.
Coordinate the work of other Analog Designers and Verification teams, audit their output, and provide guidance and direction to deliver high-quality results.
Develop basic test benches and support verification, Design For Test (DFT), and post-silicon validation activities for the products in partnership with verification and product teams.
Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams.
Align development methodologies with wider teams and drive continuous improvement to Analog Design Flow and development processes for at-scale execution.
Other:
- Embody our culture and values.

Qualifications

Required/minimum qualifications

Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
- OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
- OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
- OR equivalent experience

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
- Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. § 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation).
Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through hardware development.

Preferred Qualifications:

12+ years of experience in custom analog and mixed-signal Integrated Circuit (IC) design.
10+ years of experience owning and driving large analog and mixed-signal Intellectual Property (IP) teams to successful delivery into production.
Experience with high-speed and/or low-noise analog front-end design on IP blocks such as Analog-to-Digital and Digital-to-Analog Converters (ADCs/DACs), Phase-Locked Loops (PLLs), regulators, bandgap references, and Serializer/Deserializers (SerDes).
Proficiency in analog design flows and industry-standard tooling for circuit schematic entry, simulations, post-layout extractions, and mixed-mode simulations; conversant with robust design methodologies for reliability and aging-aware designs.
Experience with Analog Mixed-Signal (AMS) simulation across the design lifecycle, including silicon characterization of AMS blocks through release to production.
Experience coordinating work with contractors and vendors to execute analog and mixed-signal IP delivery.
Experience working with multiple stakeholders across architecture, design, layout, and silicon validation teams.
Proficiency in MATLAB for complex modeling and visualization.
Proficiency in scripting languages such as Python and Perl, including automation of simulation and data analysis environments.

#Quantum #QuantumCareers #MDQCareers

Quantum Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about **requesting accommodations.**