Principal Silicon Engineer - Networking

Microsoft Microsoft · Big Tech · Santa Clara, CA +1 · Silicon Engineering

Principal Silicon Engineer for the Data Processing Unit (DPU) team within Azure Hardware Systems & Infrastructure group. Responsible for front-end Micro-architecture and RTL implementation of networking accelerator modules. Requires Doctorate or Master's/Bachelor's with significant experience in Electrical Engineering, Computer Engineering, or Computer Science.

What you'd actually do

  1. As a Principal Silicon Engineer in the Data Processing Unit team, you will be responsible for front end Micro-architecture and RTL implementation of networking accelerator modules to solve complex problems in a datacenter.
  2. You will interact with the software team to co-develop programmable design implementation, verification, and modeling strategies.
  3. This position is expected to be highly visible and impactful.
  4. The vast breadth of domains required to build our DPU silicon gives the perfect opportunity to experience different areas of expertise.
  5. The depth required to solve complex engineering problems utilizes your experience and provides you with the perfect platform to shine and grow to the next stage in your career.

Skills

Required

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • meet Microsoft, customer and/or government security screening requirements
  • Microsoft Cloud Background Check
  • provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • successful candidate’s citizenship will be verified with a valid passport

Nice to have

  • BS and/or MS in Electrical Engineering or equivalent degree
  • 15+ years of Design verification and/or architecture experience
  • Knowledge of Ethernet, RDMA, TCP/IP, MAC/PCS, Packet forwarding, P4 pipelines and data path Networking blocks
  • Track record with the definition and development of complex SoCs
  • In depth understanding of processors and peripheral interconnect bus protocols and architectures
  • Complex subsystem verification experience that involve multiple complex design modules
  • Understanding of low power microarchitecture techniques
  • Strong knowledge of Verilog, System Verilog, UVM, C++, Python and Perl
  • Technical team management experience is plus
  • Hands on experience with VSCODE or Cursor IDEs
  • well versed with use of AI agents as an assist in coding and debugging

What the JD emphasized

  • cutting-edge, high performance, low power, scalable and programmable DPU silicon
  • front end Micro-architecture and RTL implementation
  • networking accelerator modules
  • solve complex problems in a datacenter
  • co-develop programmable design implementation, verification, and modeling strategies
  • complex SoCs
  • Complex subsystem verification experience that involve multiple complex design modules