Principal Solutions Architect – Semiconductor Test

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

This role focuses on defining and leading the technical strategy for semiconductor test, including modernizing test infrastructure and embedding data-driven intelligence. A key aspect is driving the adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization within the semiconductor manufacturing and product engineering domains. The role requires extensive experience in semiconductor test engineering and a strong background in DFT architectures, with a preference for applying ML/AI to yield analysis.

What you'd actually do

  1. Define the comprehensive test development strategy across wafer-level (probe/ATE) and package/final/qual test for new and existing product families.
  2. Lead architectural trade-off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow.
  3. Establish architectural guidelines for the test program, Test Methods/Class structure, modularity, and reuse across ATE platforms (Advantest, Teradyne, etc.).
  4. Serve as the senior liaison between build and test engineering for DFT architecture decisions — scan, BIST, JTAG, boundary scan, and embedded compression.
  5. Influence SoC and IP build reviews to ensure testability, observability, and debug-ability

Skills

Required

  • Semiconductor test engineering
  • ATE platform architecture
  • Test program development
  • DFT methodology
  • Yield analysis
  • Test data/ML analytics
  • Advantest V93000
  • Teradyne UltraFLEX/ETS
  • Scan compression
  • MBIST
  • LBIST
  • JTAG
  • Python
  • Perl
  • C++
  • MSEE, MSCE, MSCS, or related field (or equivalent experience)

Nice to have

  • Mixed-signal test
  • RF test
  • High-speed I/O test
  • Test data formats (STDF, ATDF)
  • Analytics tools (JMP, Spotfire, or custom)
  • Advanced packaging test challenges (2.5D/3D, chiplets, KGD)
  • SEMI standards committees
  • ATE vendor co-development programs
  • Ph.D or equivalent experience

What the JD emphasized

  • 15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
  • Extensive knowledge in at least three of the following areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.

Other signals

  • Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.
  • Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test.