Product Engineer, Silicon

Google Google · Big Tech · New Taipei, Banqiao District, New Taipei City, Taiwan +1

Develop and deploy productization solutions for custom silicon, enabling manufacturing at fabrication plants and assembly/test sites. Integrate SoC technologies into devices, facilitate ATE/SLT manufacturing testing, and validate performance. Work with cross-functional teams on test coverage, cost efficiencies, digital/mixed signal tests, automation, data analysis, yield analysis, silicon debug, reliability qualification, and manufacturing ramp. Partner on releasing production test solutions into mass production.

What you'd actually do

  1. Perform SoC Artificial Intelligence (AI)-centric product specifications and Design for testing (DFT) architecture reviews and generate New Product Introduction (NPI) characterization, test, or manufacturing plans.
  2. Support test hardware design (e.g., probe card, Load board) requirements, ATE/SLT test program review, and work for test coverage.
  3. Perform Die/Package level bring-ups, troubleshoot different failure modes and help resolve issues by collaborating with cross-functional teams.
  4. Support Outsourced Assembly and Test (OSAT) bring-up, ATE/SLT manufacturing test programs releases, and meet test cost goals.
  5. Manage NPI and Manufacturing Return Materials/Merchandise Authorizations (RMAs) to achieve TurnAround Times (TATs) and provide lot dispositions.

Skills

Required

  • Bachelor's degree in Electrical Engineering, Semiconductor Processing, or a related field, or equivalent practical experience.
  • 4 years of experience in VLSI technologies, product and test engineering, and semiconductor processing.
  • Experience in Integrated Circuit (IC) qualification, data review, production release, system level testing, test time reduction and yield improvement.
  • Experience with Yield and Fail Pareto Analysis using JMP, Exensio, Datapower or O+.

Nice to have

  • 8 years of experience in VLSI technologies, Product and Test Engineering, Semiconductor processing.
  • Experience in Test and Design for test (DFT) techniques, and with structural tests such as Scan/ATPG, JTAG, Memory BIST and sensors such as PVT/temperature/current/droop sensors, etc.
  • Experience with test chip design, development and testing methodologies.
  • Experience with advanced packaging such as 2.5d, 3d, InFo.
  • Familiar with Automatic Test Equipment (ATE) test platforms such as Advantest 93K , Teradyne UltraFlex SOC test system.
  • Knowledge of reliability stress, device qualification and associated processes.

What the JD emphasized

  • SoC Artificial Intelligence (AI)-centric product specifications
  • Automated Test Equipment (ATE)/System Level Testing (SLT) manufacturing testing
  • silicon debug
  • reliability qualification