What you'd actually do

Lead ASIC projects for Microsoft's quantum solutions, partnering with IP owners to develop IP blocks, integrating them at the SoC top level, and working with Digital Verification (DV), Synthesis, Design-For-Test (DFT), and Physical Design teams to prepare the SoC for tapeout.

Own post-silicon test and scan, validation, device characterization, and the path to production.

Coordinate the work of engineers, contractors, and contracting agencies delivering portions of the SoC.

Drive microarchitecture and Register-Transfer-Level (RTL) design, coding, and verification of complex IP blocks, with an emphasis on meeting stringent power, performance, and timing goals.

Develop constraints, power intent, synthesis, and static checks including LINT, Clock-Domain Crossing, and Reset-Domain Crossing. Build basic test benches and support verification, DFT, and post-silicon validation activities alongside verification and product teams.

Skills

Required

ASIC project leadership
SoC and IP microarchitecture specification
RTL design and verification
Digital Verification (DV)
Synthesis
Design-For-Test (DFT)
Physical Design
post-silicon test and validation
device characterization
project management
collaboration with cross-functional teams
understanding of power, performance, and timing goals
constraint development
power intent
static checks (LINT, CDC, RDC)
test bench development
database and repository management
development methodology alignment

Nice to have

Quantum computing hardware
cryo-electronics
analog mixed-signal design

Overview

Microsoft's Quantum team is dedicated to developing the first scalable, fault-tolerant quantum computer and is leading progress in areas ranging from quantum hardware and error correction to comprehensive integration with Azure. Our team comprises an accomplished and diverse international team focused on constructing a scalable quantum computing system. Our full-stack strategy encompasses breakthrough developments, spanning the physics of quantum devices to scalable readout and control infrastructures powered by cryo-electronics.

The Microsoft Quantum program aims to transform the future of computing and tackle challenges that are currently beyond reach. We are entering a pivotal phase of accelerated growth in quantum computing, and this position presents a unique opportunity to contribute meaningfully to a transformative technology, such as the Application Specific Integrated Circuits developed by this team.

As a Quantum ASIC Project Lead on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing Microsoft's quantum ASIC infrastructure, defining System-on-Chip (SoC) and Intellectual Property (IP) microarchitecture specifications and driving employees, contingent staff, and external vendors to deliver high-quality designs through tapeout and production.

Across the program lifecycle, you will partner with cross-functional teams spanning architecture, quantum, verification, analog, physical design, and vendors to ensure designs meet specifications and are successfully implemented and verified. This role demands strong technical depth, excellent communication, and the ability to navigate complex design challenges in a collaborative environment.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Responsibilities

Lead ASIC projects for Microsoft's quantum solutions, partnering with IP owners to develop IP blocks, integrating them at the SoC top level, and working with Digital Verification (DV), Synthesis, Design-For-Test (DFT), and Physical Design teams to prepare the SoC for tapeout.
Own post-silicon test and scan, validation, device characterization, and the path to production.
Coordinate the work of engineers, contractors, and contracting agencies delivering portions of the SoC.
Drive microarchitecture and Register-Transfer-Level (RTL) design, coding, and verification of complex IP blocks, with an emphasis on meeting stringent power, performance, and timing goals.
Develop constraints, power intent, synthesis, and static checks including LINT, Clock-Domain Crossing, and Reset-Domain Crossing. Build basic test benches and support verification, DFT, and post-silicon validation activities alongside verification and product teams.
Collaborate effectively with architects, analog mixed-signal designers, verification engineers, physical design and DFT teams, and other front-end designers.
Set up and manage databases and flows for SoC and IP repositories. Align development methodologies across teams and drive continuous improvement of RTL processes for at-scale execution.
Other
- Embody our culture and values.

Qualifications

**Required/minimum qualifications **

Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
- OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
- OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
- OR equivalent experience.

**Other Requirements: **

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
- Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. § 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation).
Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through hardware development.

**Preferred qualifications **

15+ years of experience in digital design, including microarchitecture specification and RTL coding in Verilog and SystemVerilog.
8+ years of hands-on experience with synthesis, timing constraints, and Power/Performance/Area (PPA) trade-offs.
5+ years of experience leading SoC integration through successful ASIC tapeouts, including program status generation and reporting.
Demonstrated proficiency in RTL design and front-end design methodologies.
Proven track record closing Clock-Domain Crossing (CDC), Reset-Domain Crossing (RDC), and LINT checks, plus post-silicon debug.
Experience integrating Central Processing Units (CPUs), analog IP, and standard bus interfaces such as Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), Inter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI), and Joint Test Action Group (JTAG).
Experience coordinating and managing SoC execution with external vendor teams.
Proficiency scripting in Python and/or Perl to automate engineering and design workflows.
Experience designing and building AI agents or copilots that assist with engineering tasks such as environment setup, log triage, or measurement report generation.
Track record of integrating AI-assisted solutions into design flows to improve productivity and quality.

#Quantum #QuantumCareers #MDQCareers

Quantum Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about **requesting accommodations.**