Reliability/dfx Engineer

OpenAI OpenAI · AI Frontier · San Francisco, CA · Scaling

OpenAI's Hardware organization is seeking a cross-stack engineer to make ML systems reliable at scale. This role will work closely with chip design, platform design, and hardware health teams to architect, implement, and deploy reliable next-generation AI accelerator systems. Responsibilities include overseeing DFX architecture, building system-level reliability models, collaborating on DFX features, and partnering with hardware health teams for continuous improvement. Requires deep expertise in reliability across the chip/platform stack, ML chip/platform architecture, and ML workload characteristics.

What you'd actually do

  1. Oversee DFX architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to enhance reliability and fault tolerance. DFX includes design for testability, reliability, availability, and serviceability of high-performance AI hardware.
  2. Build system-level reliability models grounded in empirical data to guide organization-wide DFX and reliability strategy. This requires a detailed understanding of chip and system architecture, design, implementation, and component-level reliability.
  3. Collaborate with chip and platform architecture/design teams to explore and implement DFX features, including the specification and implementation of digital/mixed-signal IP, firmware/system software, and DFX methodology (in partnership with engineering teams).
  4. Partner with hardware health and platform design teams to continuously improve reliability and fault tolerance in NPI and HVM. This includes optimizing operating conditions, designing experiments, and performing data analysis to drive continuous, data-driven improvements across the stack.
  5. Serve as the DFX/reliability champion and evangelist to align the broader industry ecosystem with OpenAI’s requirements and roadmap.

Skills

Required

  • BS with 15+ years, MS with 10+ years, or PhD with 3+ years of relevant industry experience focused on reliability across the chip/platform stack.
  • Hands-on experience with RTL design and DFT is required
  • Detailed understanding of ML chip and platform architecture and ML workload characteristics is required.
  • Strong fundamentals in reliability modeling, with hands-on skills in empirical data analysis.

Nice to have

  • physical implementation and/or silicon ATE experience is preferred.

What the JD emphasized

  • reliability
  • DFX
  • chip and platform stack
  • ML chip and platform architecture
  • ML workload characteristics
  • RTL design and DFT is required