Reliability Verification Technical Manager

Intel Intel · Semiconductors · Bangalore, India

This role manages a team of engineers responsible for developing, validating, and optimizing Process Design Kits (PDKs) and design methodologies for Intel's advanced process nodes. The focus is on ensuring the quality and robustness of PDK collateral for internal and external design communities, particularly in ASIC EM/IR, ESD PERC, and High Voltage domains. The manager will drive innovation in tools and flows, collaborate with manufacturing and design teams, and conduct root cause analyses for issues.

What you'd actually do

  1. Lead, develop, and manage a team of PDK and design methodology engineers to deliver robust PDK collateral for internal and external design communities for ASIC EM/IR, ESD PERC and High Voltage domain check methodologies .
  2. Oversee quality assurance activities, ensuring validation issues are logged in a ticketing database, tracked, and resolved prior to release.
  3. Drive innovation in tools, flows, and methods to optimize design functions such as circuit design, physical design, and verification.
  4. Collaborate with manufacturing process engineering and design teams to align methodologies with process technology requirements.
  5. Conduct root cause analyses for PDK/TFM issues related to PDK Collaterals, Tool and Flow methodologies and implement corrective actions to close gaps.

Skills

Required

  • 10+ years of industry experience with a Bachelor's degree, 8+ years with a Master's degree, or 5+ years with a PhD.
  • Technical expertise in ASIC EM and IR Flow methodologies us Synopsys RHSC/Cadence Voltus
  • Experience in PDK development and quality assurance.
  • Experience in ESD PERC flow methodologies using ICV/Calibre or Pegasus
  • Proficiency in EDA tools from multiple vendors, as well as PDK contents including variation and aging.
  • Strong skills in planning, prioritization, and delegation to manage a high-functioning team.
  • 2+ year experience in managing a team.

Nice to have

  • Good Experience with ASIC EM and IR flow methodologies using Synopsys RHSC and Cadence Voltus ; Experience in technology file developments and and Tool certification process.
  • Experience in ESD PERC flow methodologies and ESD PERC runset development.
  • Proven ability to build and evolve organizational capabilities.
  • Exposure to advanced IC manufacturing process nodes and standard engineering practices such as reliability, variation, and low-power design.
  • Effective communication skills for engaging across organizational levels, customers, and suppliers.
  • Motivation to continuously improve organizational processes and enhance team offerings.