Research Engineer, Chip Design RL (reinforcement Learning)

Anthropic Anthropic · AI Frontier · San Francisco, CA · AI Research & Engineering

Research Engineer role focused on applying Reinforcement Learning to chip design, specifically for agentic RTL generation, design verification, and physical design optimization. The role involves inventing RL environments, optimizing EDA tools, conducting experiments, and delivering work into research and production training runs. Requires expertise in ASIC/FPGA design and familiarity with EDA tools, with strong candidates having RL experience.

What you'd actually do

  1. Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.
  2. Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
  3. Conduct experiments and shape our roadmap.
  4. Deliver your work into research and production training runs.
  5. Collaborate with other researchers and engineers across and outside Anthropic.

Skills

Required

  • ASIC or FPGA design
  • RTL
  • design verification (UVM, formal methods, coverage-driven)
  • physical design (synthesis, place-and-route, timing closure)
  • PPA optimization
  • DFT
  • ECOs
  • EDA tools and processes
  • experience going from spec to silicon

Nice to have

  • reinforcement learning
  • evaluations or environments
  • tooling or automation around chip design flows
  • ML accelerators or high-performance compute hardware
  • high-level synthesis or architecture simulators

What the JD emphasized

  • expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs
  • fluent with industry EDA tools and processes
  • taped out chips and have experience going from spec to silicon

Other signals

  • Reinforcement Learning
  • Agentic RTL generation
  • Chip design expertise