Research Engineer, ML H-w/s-w Codesign

Meta Meta · Big Tech · Sunnyvale, CA

Research Engineer focused on ML hardware/software codesign for on-device AI in AR/VR. Develops novel solutions for efficient training and inference of vision and language models, optimizing for compute, power, latency, and real-time constraints. Involves algorithm development, network design, hardware architecture, model compression, and integration with AI accelerators.

What you'd actually do

  1. Identify and solve multi-discipline ML acceleration problems involving algorithms, network design, hardware architecture, multimodal AI and AR/VR use cases.
  2. Work across hardware and software, to solve co-design problems with other Research scientists working in this area
  3. Codesign and invent novel ML accelerator and system architecture solutions, and facilitate the integration of algorithms and software to utilize these enhancements
  4. Develop state-of-the-art model compression and scalability techniques using Numerics, pruning, distillation etc
  5. Optimize models on hardware accelerators to achieve optimal performance given various real time latency and power constraints

Skills

Required

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • PhD in Electrical Engineering, Computer Science, or equivalent experience
  • Experience developing AI-System infrastructure, AI algorithms or AI hardware acceleration in C/C++ or Python
  • Experience with PyTorch, TensorFlow or similar machine learning toolsets
  • Experience working and communicating cross-functionally in a team environment
  • Experience or knowledge of on-device algorithm development including hardware-aware ML models and/or optimizing ML compilers for efficient deployment on AI accelerators
  • Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
  • Experience or knowledge of training/inference of Large scale AI models - CV and/or LLMs
  • Demonstrated research and engineering experience via an internship, work experience, coding competitions, or widely used contributions in open source repositories (e.g. GitHub)
  • Experience or knowledge of architecting ML hardware accelerators and systems
  • Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
  • Proven track record of achieving significant results as demonstrated by grants, fellowships, patents, as well as publications at leading workshops, journals or conferences such as ICLR, NeurIPS, CVPR, ACL, ICML, MLSys, ISCA, MICRO, DAC, ASPLOS etc
  • Experience evaluating alternative system or algorithm designs by analyzing trade-offs in performance, power, and latency to recommend a solution
  • Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies

What the JD emphasized

  • novel approaches not yet established in the industry
  • novel ML accelerator and system architecture solutions
  • state-of-the-art model compression and scalability techniques
  • optimal performance given various real time latency and power constraints
  • data-driven analysis and clear communication of trade-offs
  • Apply in-depth knowledge of how the ML acceleration interacts with the other systems around it
  • stay updated with latest research advancements in the field of ML acceleration
  • publications at leading workshops, journals or conferences such as ICLR, NeurIPS, CVPR, ACL, ICML, MLSys, ISCA, MICRO, DAC, ASPLOS etc

Other signals

  • ML models
  • hardware acceleration
  • software systems
  • on-device inference
  • vision and language models
  • model compression
  • scalability techniques
  • real time latency
  • power constraints