Rtl / Circuit Ip Design Engineer

AMD AMD · Semiconductors · San Jose, CA · Engineering

This role is for an RTL/Circuit IP Design Engineer at AMD, focusing on the implementation of new and existing features for programmable embedded IP. Responsibilities include collaborating with architects and engineers, authoring documentation, estimating implementation time, building verification tests, debugging failures, and reviewing coverage metrics. The role requires proficiency in IP level RTL implementation, debugging RTL code, Verilog/System Verilog, and circuit design concepts. Experience with UVM, Linux/Windows, automation, analytical problem-solving, UPF, clocking, reset, and power domain crossings is preferred. Scripting languages like Python are also beneficial.

What you'd actually do

  1. Collaborate with architects, hardware engineers, and software engineers to understand the new features to be implemented
  2. Author implementation documentation, accounting for interactions with other features, the hardware, and the software modeling use cases
  3. Estimate the time required to implement the new features, collaborate with design verification test development, and any execute required changes based on cross functional feedback
  4. Build the directed and random verification tests
  5. Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues

Skills

Required

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

  • Proficient in IP level RTL implementation
  • Proficient in debugging RTL code using simulation tools
  • Proficient in navigating UVM generated test results and working in Linux and Windows environments
  • Experienced with Verilog and System Verilog
  • Strong understanding of circuit design concepts, translating circuit designs in an optimal way to either custom implementations or with best practices for RTL synthesis
  • Automating workflows in a distributed compute environment.
  • Proficient in analytical problem solving, specifically with troubleshooting component designs (e.g., timing analysis, constraint setting)
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Strong background in developing and verifying SAPR constraints
  • Good understanding and hands-on experience in UPF concepts
  • Good working knowledge of clocking, reset, and power domain crossings with some related experience.
  • Scripting language experience: Python, Perl, Ruby, Makefile, shell preferred.
  • Exposure to leadership or mentorship is an asset
  • Experience with circuit macro generation, characterization, and collateral release processes
  • Desirable assets with prior exposure to high speed interfaces