Rtl & Co-design Engineer (junior)

OpenAI OpenAI · AI Frontier · San Francisco, CA · Scaling

The role focuses on designing and implementing RTL for custom AI accelerators, working closely with software and research partners on hardware/software co-design. It involves microarchitecture, RTL production, performance modeling, and collaboration with various engineering teams across the silicon lifecycle.

What you'd actually do

  1. Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems
  2. Contribute to architectural studies including performance modeling and feasibility analysis.
  3. Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.
  4. Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.
  5. Build and review performance and functional models to validate design intent.

Skills

Required

  • RTL in Verilog/SystemVerilog
  • hardware design models or architectural simulators
  • cross-functionally with architecture, ML systems, compilers, and verification teams
  • problem-solving skills
  • think across abstraction layers, from algorithms to circuits

Nice to have

  • computer architecture
  • AI/ML hardware–software co-design
  • workload analysis
  • dataflow mapping
  • accelerator algorithm optimization
  • industry-standard design tools (lint, CDC/RDC, synthesis, STA)
  • massive-scale hardware systems

What the JD emphasized

  • production-quality RTL
  • track record of delivering complex blocks to tape-out