Rtl & Codesign Engineer

OpenAI OpenAI · AI Frontier · San Francisco, CA · Scaling

This role focuses on designing and implementing RTL for custom AI accelerators, working closely with architecture, verification, and ML engineers. It involves microarchitecture, RTL production, performance modeling, and hardware/software co-design for AI workloads.

What you'd actually do

  1. Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems
  2. Contribute to architectural studies including performance modeling and feasibility analysis.
  3. Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.
  4. Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.
  5. Build and review performance and functional models to validate design intent.

Skills

Required

  • RTL Engineer
  • Verilog/SystemVerilog
  • computer architecture
  • AI/ML hardware–software co-design
  • workload analysis
  • dataflow mapping
  • accelerator algorithm optimization
  • hardware design models
  • architectural simulators
  • AI/ML or high-performance compute systems
  • lint
  • CDC/RDC
  • synthesis
  • STA
  • cross-functional collaboration
  • problem-solving
  • algorithms to circuits

Nice to have

  • AI-native silicon
  • custom design tools and methodologies
  • performance modeling
  • feasibility analysis
  • simulator
  • compiler teams
  • DV
  • PD
  • timing closure
  • area/power targets
  • design reviews
  • documentation
  • bring-up support
  • full silicon lifecycle

What the JD emphasized

  • production-quality RTL
  • track record of delivering complex blocks to tape-out
  • hardware design models or architectural simulators
  • AI/ML or high-performance compute systems