Rtl Design Engineer, Machine Learning Accelerators

Google Google · Big Tech · Sunnyvale, CA +1

This role focuses on the RTL design of Machine Learning Accelerators (TPUs) for Google's AI/ML applications. The engineer will design and verify complex digital designs with a focus on TPU architecture and its integration within AI/ML-driven systems, contributing to custom silicon solutions.

What you'd actually do

  1. Understand the overall application of the chip, proposing and developing improvements in overall design.
  2. Design and document one or more blocks of an ASIC, including functionality and timing.
  3. Work with software teams on functionality, interfaces, and documentation.

Skills

Required

  • Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience.
  • 4 years of experience with custom silicon design (e.g., SoCs, ASICs, etc.).
  • Experience with RTL design using Verilog or SystemVerilog.

Nice to have

  • Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture.
  • Experience interacting with software, architecture, and other cross-functional teams.
  • Experience with a scripting language (e.g., Python or Perl)
  • Experience applying engineering best practices (e.g., code review, testing, refactoring).
  • Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms.
  • Knowledge of high performance and low power design techniques.

What the JD emphasized

  • custom silicon solutions
  • TPU architecture
  • AI/ML applications
  • AI/ML hardware acceleration

Other signals

  • custom silicon solutions
  • TPU architecture
  • AI/ML applications
  • AI/ML hardware acceleration