Rtl Silicon Design Engineer

AMD AMD · Semiconductors · Hyderabad, India · Engineering

RTL Silicon Design Engineer at AMD focusing on IP cores for high-performance products in networking, security, and storage. The role involves developing synthesizable RTL, utilizing AI tools for design productivity, collaborating with cross-functional teams, and supporting various design stages from specification to timing closure. Experience with AI-powered tools for RTL design is preferred.

What you'd actually do

  1. Develop synthesizable RTL for IP cores targeting advanced technology nodes
  2. Utilize modern AI tools to achieve a high level of RTL design productivity through code generation, refactoring, documentation, and debug
  3. Collaborate directly with IP Architecture, IP Verification, and SoC integration teams
  4. Contribute to design specifications for IP cores
  5. Resolve IP simulation regression failures through close collaboration with IP Verification Team and work with Verification Team members to ensure achievement of verification quality metrics

Skills

Required

  • Verilog RTL coding
  • front-end design flows
  • data networking and communications protocols
  • ASIC architecture and RTL design
  • EDA design processes
  • delivering ASIC and/or FPGA solutions to the market
  • design and code innovative, high quality IP products
  • team player
  • excellent written and verbal communication skills
  • collaborating across multiple design sites and time zones
  • strong analytical and problem-solving skills
  • self-starter
  • desire to learn
  • ability to solve complex, novel, and non-recurring problems
  • attention to details
  • working amongst a multi-disciplinary team
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

  • AI tools for productivity
  • AI-powered tools (VS Code, GitHub Copilot, Cursor) for RTL design
  • simulation and debugging with functional verification tools
  • standard bus/interface protocols (i.e. AXI, AHB, AMBA)
  • modern, complex networking architecture and digital design
  • networking protocols (such as Ethernet) and standards for digital communication systems, optical communications, and packet processing applications
  • encryption protocols (such as MACsec and IPsec) and security technologies for digital communication systems
  • Proficient with workplace AI tools (Microsoft M365 Copilot, ChatGPT, Atlassian Rovo)
  • Proficient with scripting languages such as Python, Perl, TCL, Makefile, and csh/bash
  • 8 Years experience in RTL (Verilog / System Verilog) ASIC design experience through implementations targeting leading edge ASIC technologies
  • Proven experience with industry-leading ASIC design tools, synthesis tools, flows, and timing closure
  • Experience executing design checks such as lint, CDC, and LEC using industry standard ASIC tools
  • Skilled in simulation and debugging with functional verification tools from Synopsys, Cadence, and/or Siemens (Mentor) including Gate-level simulations

What the JD emphasized

  • AI tools for productivity
  • RTL coding
  • front-end design flows
  • data networking and communications protocols
  • ASIC architecture and RTL design
  • EDA design processes
  • delivering ASIC and/or FPGA solutions to the market
  • design and code innovative, high quality IP products
  • AI-powered tools (VS Code, GitHub Copilot, Cursor) for RTL design
  • simulation and debugging with functional verification tools
  • standard bus/interface protocols (i.e. AXI, AHB, AMBA)
  • modern, complex networking architecture and digital design
  • networking protocols (such as Ethernet) and standards for digital communication systems, optical communications, and packet processing applications
  • encryption protocols (such as MACsec and IPsec) and security technologies for digital communication systems