Senior Architect

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +2

NVIDIA is seeking an experienced Senior Architect to join their memory system architecture team. The role involves driving architecture and micro-architecture development for NVIDIA's SOCs, focusing on performance, power efficiency, and complexity. Responsibilities include performance modeling, simulation, analysis, and debugging of memory systems for various applications including deep-learning, autonomous vehicles, and robotics.

What you'd actually do

  1. Driving development of architecture and micro-architecture to improve the state-of-the-art in memory systems optimizing along the axes of performance, power efficiency, complexity, area, effort, and schedule.
  2. Performance modeling and simulation of features to improve memory system performance and efficiency.
  3. Implementing and maintaining detailed and high-level performance models.
  4. Analyzing benchmarks, application workloads, and performance simulation results to identify tradeoffs in areas of micro-architectural optimizations.
  5. Debug performance and functional issues with high-level models, RTL simulation, and silicon.

Skills

Required

  • M.S. or Ph.D. in CS, CE, or EE (or equivalent experience)
  • 5+ years experience in SoC or memory system architecture and performance
  • Deep understanding of memory subsystems – caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation
  • Strong communication and interpersonal skills
  • Software development experience with C++, python and/or perl

Nice to have

  • Verilog or SV/UVM
  • Significant experience with performance modeling or performance verification
  • Experience debugging and solving complex performance issues

What the JD emphasized

  • track record of architecture development
  • 5+ years experience in SoC or memory system architecture and performance
  • Deep understanding of memory subsystems – caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation