Senior Asic Design and Sta Engineer

NVIDIA NVIDIA · Semiconductors · Bangalore, India

NVIDIA is seeking a Senior ASIC Design and STA Engineer to join their Networking Silicon engineering team. The role involves full chip and/or chiplet level Static Timing Analysis (STA) convergence, floor plan and clock planning, optimizing signoff flows, and timing integration. The engineer will work closely with design and DFT teams to define and implement constraints. The role requires 5+ years of experience in physical design and STA, familiarity with EDA tools, and hands-on STA experience using Synopsis Primetime.

What you'd actually do

  1. Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
  2. Take part in top level floor plan and clock planning.
  3. Optimize, together with CAD signoff flows and methodologies.
  4. Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.
  5. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.

Skills

Required

  • B.SC/ M.SC in Electrical Engineering/Computer Engineering
  • 5+ years of experience in physical design and STA
  • Proven experience in RTL2GDS and STA design and convergence
  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)
  • Hands on STA experience from early stages to signoff using Synopsis Primetime.
  • Deep knowledge in timing concepts

Nice to have

  • Great teammate