Senior Asic Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Senior ASIC Design Engineer to design and implement SoCs and GPUs, focusing on micro-architecture and build implementation of NOC/interconnect Xbar. The role requires expertise in logic design, Verilog/System-Verilog, ASIC flow, and collaboration across engineering teams.

What you'd actually do

  1. As a key member of our design team, you will be responsible for the micro-architecture and build implementation of NOC/interconnect Xbar.
  2. Micro-architect features to meet area, performance, and power requirements.
  3. Deliver a fully verified build by working closely with verification engineers.
  4. Deliver a synthesis/timing clean build to ensure a routable and physically implementable design.
  5. Collaborate with architects, verification engineers, software engineers, and physical build engineers to accomplish your goals.

Skills

Required

  • Bachelor's or Master’s Degree in Electrical Engineering or Computer Engineering, or equivalent experience.
  • 8+ years of build/RTL experience working on complex units in xbar/memory system.
  • Highly proficient in logic design, Verilog and/or System-Verilog, with a solid understanding of Computer Architecture and Digital Systems build.
  • A deep understanding of ASIC flow including RTL, verification, logic synthesis, timing analysis, ECO, and post silicon debug.
  • Strong interpersonal and communication skills to collaborate across teams.
  • Prior experience building arbiters, scheduling, synchronization, bus protocols, interconnect networks and/or switches.
  • Familiarity with architecture concepts and implementation of arbitration policies, interconnection routing policies/deadlock avoidance, and virtual channels.
  • Good debugging and analytical skills.

What the JD emphasized

  • 8+ years of build/RTL experience working on complex units in xbar/memory system.