Senior Asic Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior ASIC Design Engineer role at NVIDIA, focusing on the design, implementation, and verification of high-performance RTL for SoCs and GPUs. Responsibilities include architecture, micro-architecture, RTL design, synthesis, logic and timing verification, and collaboration with development teams. Requires a Bachelor's or equivalent experience with 5+ years in VLSI and Computer Architecture, expertise in Verilog/System Verilog, and proficiency in Perl/Python/C/C++.

What you'd actually do

  1. Crafting architecture and micro-architecture, as well as conducting RTL design and synthesis.
  2. Performing logic and timing verification using advanced CAD tools and semiconductor process technologies.
  3. Participating in the verification of builds through sophisticated methodologies, including the development of design properties and assumptions for formal verification.
  4. Collaborating closely with several ASIC development teams, ensuring seamless communication and coordination to successfully implement build requirements.

Skills

Required

  • Bachelor's or equivalent experience, or a Master's degree or equivalent experience in a relevant field, with 5+ years of experience
  • proven hardware engineering background with a focus on VLSI and Computer Architecture
  • Expertise in Verilog, System Verilog, or similar HDL
  • proficiency in programming languages such as Perl/Python and C/C++
  • Solid experience with logic synthesis and timing analysis
  • Familiarity with build and verification tools, including simulation tools like VCS, and debug tools like Debussy and GDB
  • Experience with test bench environments for both unit and system-level verification, including random stimulus, functional coverage, and assertion-based verification methodologies
  • Excellent debugging and analytical skills
  • Strong interpersonal skills, with the ability to work effectively with both on-site and remote teams

Nice to have

  • knowledge of high-speed energy-efficient data paths is an advantage