Senior Asic Design Engineer - Agentic AI

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +2

NVIDIA is seeking Senior ASIC Design Engineers with experience in agentic AI to design and implement SoC's and GPU's. The role involves developing agentic AI solutions for micro-architecture, RTL implementation, and verification, as well as deploying LLM-powered solutions for engineering assistants and multi-turn, multi-modal dialogue systems. Requires experience in ASIC design flow, Python, fine-tuning LLMs, multi-agent systems, RAG, and vector databases.

What you'd actually do

  1. As part of the AI for Chip Design team, you will develop agentic AI solutions to craft the micro-architecture, implement the RTL, and deliver a fully verified, synthesis/timing clean design.
  2. Drive impact by designing and deploying LLM-powered solutions for engineering assistants and multi-turn, multi-modal dialogue systems.
  3. Make a difference by using AI technologies to tackle complex problems in chip design, driving innovation and meaningful impact across the industry.
  4. As a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications.
  5. Collaborate and coordinate with other designers as well as tool and flow owners to make sure design guidelines and agentic solutions meet their requirements.

Skills

Required

  • Master's or PhD degree in Electrical Engineering, Computer Science/Engineering, or a related field (or equivalent experience).
  • 8+ years of meaningful work experience.
  • Experience in micro-architecture and RTL development (Verilog) in complex designs.
  • Deep understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
  • Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required.
  • Proficiency in rapid prototyping using Python with strong foundational knowledge of data structures, algorithms, and software engineering principles.
  • Experience with fine-tuning large language models, building advanced multi-agent systems, RAG pipelines and vector databases.
  • Strong analytical, communication, and interpersonal skills, with a proven track record to thrive in dynamic, product-focused, and distributed teams.
  • A proactive approach to problem-solving and a willingness to acquire new skills and knowledge as needed to achieve results.

What the JD emphasized

  • Experience with fine-tuning large language models, building advanced multi-agent systems, RAG pipelines and vector databases.
  • Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required.
  • Experience in micro-architecture and RTL development (Verilog) in complex designs.
  • Deep understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.

Other signals

  • AI for chip design
  • agentic AI solutions
  • LLM-powered solutions for engineering assistants