Senior Asic Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior ASIC Design Engineer responsible for micro-architecture and digital design implementation of various innovative IPs for hardware security, clocking, voltage regulation, and silicon correlation. Collaborates with Architects, Circuit Designers, and Verification engineers to deliver next-generation solutions. Develops scalable RTL designs, executes synthesis, performs timing analysis, functional verification, CDC checks, and formal equivalence. Supports post-si bringup and debug activities, and develops tools and flows including Agentic AI flows.

What you'd actually do

  1. You will be responsible for the micro-architecture and digital design implementation of various innovative IPs for hardware security, clocking, voltage regulation and silicon correlation.
  2. Collaborate with Architects, Circuit Designers and Verification engineers to deliver a world-class and next-geration solution.
  3. In this role, you will have the opportunity to develop scalable RTL designs, execute synthesis and perform timing analysis using innovative CAD tools and the latest process technologies in the industry
  4. Work on functional verification, perform CDC checks and formal equivalence.
  5. Support post-si bringup and debug activities
  6. Develop and craft tools and flows including Agentic AI flows as necessary in support of design activities

Skills

Required

  • BS (or equivalent experience) in Electrical Engineering, Computer Engineering, or a related degree
  • 3+ years of relevant proven experience
  • background in logic design
  • Verilog
  • System-Verilog
  • deep understanding of physical design and VLSI
  • Experience with multiple clock domains and asynchronous interfaces
  • Exposure to Digital Systems design and computer architecture
  • Programming skills in PERL or Python
  • Excellent communication skills
  • interpersonal skills

Nice to have

  • advanced degrees (MS, PhD)
  • Experience with all stages of ASIC design flow including front end design and verification, DFT, timing analysis, ECO, ATE test development, post-si bringup & debug
  • Good understanding of behavioral real number modeling and low level digital or mixed signal design concepts
  • Strong knowledge or work experience in Mixed signal and custom designed IPs solutions
  • Proficiency in scripting language, such as, Perl, Tcl, Make files and automation methods/algorithms

What the JD emphasized

  • 3+ years of relevant proven experience
  • Excellent communication skills and interpersonal skills are required.