Senior Asic Design Engineer - Hardware

NVIDIA NVIDIA · Semiconductors · Austin, TX

Senior ASIC Design Engineer focused on system-level IP, performance measurement methodologies, and RTL design for NVIDIA's GPUs and SOCs.

What you'd actually do

  1. Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs
  2. Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP
  3. Deliver IP and support projects by applying the performance monitoring system
  4. Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)
  5. Design and implement RTL features (microarchitecture and RTL)

Skills

Required

  • BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree
  • 3+ years of relevant industry experience
  • Strong coding skills in Perl/Python or other industry-standard scripting languages
  • RTL design (Verilog)
  • Verification (SystemVerilog)
  • System-On-Chip design/implementation flow
  • Design automation
  • Understanding of SOC architecture (CDC, multiple-power domains, performance analysis, latency, data flow)
  • Debugging and analytical skills
  • Experience with design and verification tools (synthesis, simulation, debug)
  • Communication and collaboration skills

Nice to have

  • Advanced degrees (MS, PhD)
  • Hands on experience in object-oriented programming
  • Prior design on system level IP (Clocks/DFT/Resets)
  • Experience developing methodologies used by others
  • Hands- hands-on silicon debug
  • Exposure to physical design

What the JD emphasized

  • 3+ years of relevant industry experience
  • Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chip design/implementation flow, and design automation
  • Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow