Senior Asic Design Verification Engineer - Lpu

NVIDIA NVIDIA · Semiconductors · CA +1 · Remote

Senior ASIC Design Verification Engineer to verify the design and implementation of the world's leading inference accelerator. This role involves using advanced verification methodologies, collaborating with cross-functional teams, and potentially applying machine learning to the verification flow.

What you'd actually do

  1. As a key member of our ASIC Verification team, you will verify the design and implementation of inference accelerator
  2. You will be responsible for verification of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies
  3. Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design
  4. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks
  5. Implement and optimize automated verification flows to improve productivity and efficiency

Skills

Required

  • Bachelors Degree in EE, CS or CE (or equivalent experience)
  • 8+ years of relevant industry experience
  • Background with building block and SoC level testbench utilizing strong debugging and analytical skills
  • Experience in verification using random stimulus along with functional coverage, assertion-based verification methodologies and tools
  • Expertise in SystemVerilog and Universal Verification Methodology (UVM)
  • Experience with design and verification tools (VCS, Verdi or equivalent)
  • Knowledge of ASIC design flow, from specification to GDS
  • Knowledge of applying machine learning to ASIC verification flow

Nice to have

  • Background in UPF power verification is a plus
  • Experience in netlist and DFT verification is a plus
  • Perl/Python and C/C++ programming language experience desirable

What the JD emphasized

  • 8+ years of relevant industry experience
  • Expertise in SystemVerilog and Universal Verification Methodology (UVM)
  • Knowledge of applying machine learning to ASIC verification flow

Other signals

  • inference accelerator
  • ASIC design verification
  • machine learning to ASIC verification flow