Senior Asic Floorplan Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

Senior ASIC Floorplan Design Engineer at NVIDIA, focusing on designing and optimizing floorplans for GPUs and SoCs. The role involves collaborating with architects and design leads, driving area reviews, solving timing and routing issues, and building tools for optimization. Requires a Master's degree in EE/CS/CE or equivalent, 12+ years of experience, strong VLSI/Computer Architecture background, and proficiency in Verilog, CAD methodologies, and programming languages like Python.

What you'd actually do

  1. Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
  2. Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities
  3. Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
  4. You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Skills

Required

  • Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience
  • 12+ years of relevant work experience
  • VLSI
  • Computer Architecture
  • Verilog
  • System Verilog
  • CAD methodologies
  • physical design methodologies
  • chip floorplan
  • power/clock distribution
  • packaging
  • P&R
  • timing closure
  • Python
  • Perl
  • C/C++

Nice to have

  • Experience in driving development of large scale ASIC floorplan

What the JD emphasized

  • Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience
  • 12+ years of relevant work experience
  • A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
  • Experience in Verilog, System Verilog or similar HVL
  • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
  • Python, Perl and C/C++ programming language experience
  • Experience in driving development of large scale ASIC floorplan is a huge plus.