Senior Asic-fpga Verification Engineer

Boeing Boeing · Aerospace · Bangalore, India, India

This role is for a Senior ASIC-FPGA Verification Engineer at Boeing India, focusing on designing and verifying complex digital systems for commercial and defense electronics. The responsibilities include developing testbench architectures using UVM, implementing verification components, leading technical reviews, and supporting system-level architecture exploration. A key aspect is leading AI initiatives for verification automation and reviews, though the core function is ASIC/FPGA verification.

What you'd actually do

  1. Use high-level architectural documentation along with algorithm description and implement functions for test bench architecture and test plan using UVM for IP, Subsystem and System level verification.
  2. Develop reusable testbench components like scoreboards, checkers, reference models along with UVC using SV and UVM
  3. Own quality of deliverables for verification across multiple milestones for FPGA/ASIC life cycle
  4. Architect Reusable Verification components, which can be used across FPGA/ASIC life cycle
  5. Lead, drive and collaborate technical reviews with Validation, Design and System Architecture cross functional teams.

Skills

Required

  • Digital Functional verification for ASIC and FPGA
  • IP, Subsystem and System level verification
  • UVM
  • System Verilog (SV)
  • PCIe (Transaction layer)
  • Ethernet (Mac Layer)
  • Testbench Architecture
  • Verification Architect
  • Developing and mentoring Verification engineers
  • ASIC and FPGA product Tape outs

Nice to have

  • Verification team leadership
  • Verification Architecture for ASIC and FPGA Products
  • Technical performance metrics
  • Object-oriented programming in System Verilog
  • Universal Verification Methodology (UVM)
  • Drivers, monitors, predictors, coverage model and scoreboards and UVCs
  • SVA - Assertions
  • Formal verification
  • Code and functional coverage signoff
  • Linux or Unix terminal commands
  • Scripting languages: Make, Perl, Python, shell scripts
  • Revision Control Systems: Subversion (SVN), CVS, Git
  • Power aware simulation debug
  • Gate level simulation debug
  • Avionics protocols
  • DO -254 for ASIC /FPGA
  • System C
  • TLM models

What the JD emphasized

  • considerable experience in design
  • 13 to 17 years of experience in Digital Functional verification for both ASIC and FPGA at IP, Subsystem and System level as a Lead or Verification Architect
  • 8+ years of experience in leading and owning verification Activities for Multiple ASIC and FPGA product Tape outs
  • 7+ years of experience in Developing and mentoring Verification engineers
  • 5+ years of Hands-on domain experience on PCIe (Transaction layer) and Ethernet (Mac Layer)
  • Multiple Verification tape out experience in ASIC and FPGA products
  • 5+ years of experience in doing UVM based Testbench Architecture for PCIe and Ethernet across IP/Subsystem and system level for multiple projects in ASIC and FPGA