Senior Asic Infrastructure Engineer

NVIDIA NVIDIA · Semiconductors · Toronto, ON

NVIDIA is seeking a Senior ASIC Infrastructure Engineer to define and deploy AI/ML applications for chip design, debug, and verification. The role involves collaborating with hardware design teams, architecting novel tools, and staying updated on AI/ML advancements like LLMs, RAG, and GenAI to integrate them into the company's infrastructure.

What you'd actually do

  1. Define and deploy AI and ML applications to aid chip design, debug & verification stages.
  2. Collaborate closely with our hardware chip design teams to understand their infrastructure needs and map them onto AI/LLM solutions.
  3. Architect and develop novel tools, user interfaces, and creative applications.
  4. Stay on top of latest advancements in AI/ML technologies and frameworks (LLM memories, transformers, RL, RAG, GenAI) and advocate for their integration within the company.
  5. Troubleshoot and resolve critical technical or productivity obstacles that impact team’s performance.

Skills

Required

  • BS/MS in Computer Science or Computer Engineering or Electrical Engineering or equivalent experience
  • 5+ years of relevant work experience
  • Strong software architecture, development, & testing experience.
  • Solid understanding of Linux, proficient in programming skills (ex. Python / Perl) and version control systems (P4 / git).
  • Prior exposure to RAGs (Retrieval-Augmented Generation) or MCP or LangGraph based agentic AI workflows
  • Strong problem-solving abilities and a passion for debugging
  • Excellent communication and interpersonal skills

Nice to have

  • Exposure to RTL design/verification tools (VCS or equivalent simulation tools, debug tools like Verdi) and computer architecture.
  • Experience in creating scalable AI/LLM based applications for a wide user base.
  • Experience with complete CI/CD workflow (ex. Jenkins, k8s, LSF, Docker, gitlab), interfacing with REST APIs, webservers.
  • A strong passion for continual learning and keeping abreast of new technologies and approaches in AI/ML infrastructure.

What the JD emphasized

  • Prior exposure to RAGs (Retrieval-Augmented Generation) or MCP or LangGraph based agentic AI workflows

Other signals

  • Define and deploy AI and ML applications to aid chip design, debug & verification stages.
  • Collaborate closely with our hardware chip design teams to understand their infrastructure needs and map them onto AI/LLM solutions.
  • Architect and develop novel tools, user interfaces, and creative applications.
  • Stay on top of latest advancements in AI/ML technologies and frameworks (LLM memories, transformers, RL, RAG, GenAI) and advocate for their integration within the company.