Senior Asic Physical Design Engineer, Netlisting

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

This role is for a Senior ASIC Physical Design Engineer focused on netlisting aspects of high-frequency and low-power CPUs, GPUs, and SoCs. Responsibilities include equivalence checking, asynchronous checking, logic synthesis, and timing convergence. The role requires significant experience in ASIC design flows and EDA tools, with proficiency in scripting languages. While NVIDIA is a leader in AI, this specific role is in hardware design for computing infrastructure, not direct AI model development or deployment.

What you'd actually do

  1. You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
  2. Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

Skills

Required

  • BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.
  • Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools.
  • Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
  • Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools.
  • Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
  • Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
  • Expertise and in-depth knowledge of industry standard EDA tools in related fields.
  • Proficiency in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.

Nice to have

  • Experience in logic synthesis and equivalence checking/FV.
  • Familiarity with industry tools and flow.
  • Strong hands-on debugging capability and problem-solving skills.
  • Background in DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc.
  • Experience or a strong drive to improve workflows and productivity through effective AI utilization

What the JD emphasized

  • Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools.
  • Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
  • Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools.
  • Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
  • Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
  • Expertise and in-depth knowledge of industry standard EDA tools in related fields.