Senior Asic Power Engineer - Lpu

NVIDIA NVIDIA · Semiconductors · CA · Remote

NVIDIA is seeking a Senior ASIC Power Engineer to handle full-range power-related activities including ASIC energy evaluation, power architecture, low power development, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's product lineup. The role involves supporting power analysis efforts, architecting and building system-level power features, working on power verification, validating power features on silicon, and developing power management solutions.

What you'd actually do

  1. Join the NVIDIA Power Architecture Group handling the full range of power-related activities including ASIC energy evaluation, power architecture, low power development, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's product lineup.
  2. Support power analysis efforts by aiding in the architecture, creation, verification, and correlation of power estimation models/tools for NVIDIA's products.
  3. Be part of the team that architects and builds system-level power features for optimizing the dynamic and leakage power dissipation for different use cases.
  4. Work on power verification which includes structural, functional, and power-aware verification of power features of NVIDIA products by developing test plans, writing test cases, building test bench components like monitors, assertions, and coverage points, and owning verification convergence across RTL, Gates, and Silicon.
  5. Validate the efficiency of the power features on silicon, conduct studies, and contribute to Performance/Watt improvement ideas.

Skills

Required

  • B.Tech./M.Tech (or equivalent experience)
  • over 5 years of experience in power analysis, power development, power-aware verification, UPF methodologies, and power correlation
  • Solid understanding of all power aspects, including full-chip power modeling, transistor-level leakage and dynamic characteristics in VLSI circuits
  • Strong fundamentals in digital build flow and Verilog (especially low power RTL development)
  • Familiarity with low power build techniques such as multi-VT, clock gating, power gating, voltage islands, and Dynamic Voltage-Frequency Scaling (DVFS)
  • Solid experience in power estimation methods, processes, and algorithms
  • Working experience with scripting languages like Python is a must
  • Prior experience writing SW-driven power virus tests and silicon debug is necessary
  • Excellent collaborator and prepared to work with international groups from varied cultural origins in a dynamic environment

Nice to have

  • Experience in power supply and supply noise analysis and reduction
  • Good debugging and problem-solving skills
  • Strong communication abilities
  • Solid programming skills, ideally in C++
  • Knowledge of lab equipment for power measurements, including oscilloscopes or DAQs
  • Capability to troubleshoot board-level power issues

What the JD emphasized

  • over 5 years of experience in power analysis, power development, power-aware verification, UPF methodologies, and power correlation
  • Working experience with scripting languages like Python is a must
  • Prior experience writing SW-driven power virus tests and silicon debug is necessary