Senior Asic Rtl Integration and Netlisting Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +3

Senior ASIC RTL Integration and Netlisting Engineer role at NVIDIA, focusing on physical design integration, RTL integration, synthesis, and netlist deliverables for CPUs, GPUs, and SoCs. Requires significant experience in RTL integration, netlisting, logic synthesis, and gate-level netlist verification, with expertise in EDA tools. Familiarity with AI tools is a plus.

What you'd actually do

  1. You will drive physical design integration and implementation of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level
  2. Drive RTL integration, synthesis, along with all physical netlist deliverables across various milestones
  3. Drive formal equivalence checking, netlist quality checks, asynchronous checking including clock domain crossing checks and MTBF analysis, etc.

Skills

Required

  • BS (or equivalent experience) in Electrical or Computer Engineering with 8+ years’ experience or MS (or equivalent experience) with 5+ years’ experience in RTL integration and netlisting domains
  • Strong understanding of RTL and RTL hierarchy and associated infrastructures
  • Hands on experience with logic synthesis and associated verification such as equivalence checking
  • Background in gate level netlist verification and completeness with respect to power, testability, etc
  • Expertise and in-depth knowledge of industry standard EDA tools

Nice to have

  • Expertise in understanding on clock-domains, async interfaces and MTBF analysis
  • Solid understanding of Physical Design flows, design constraints, timing and power convergence
  • Proficiency in programming/scripting languages (Python, TCL etc)
  • AI tools (Cursor, Copilot, etc)

What the JD emphasized

  • 8+ years’ experience or MS (or equivalent experience) with 5+ years’ experience in RTL integration and netlisting domains
  • Strong understanding of RTL and RTL hierarchy and associated infrastructures
  • Hands on experience with logic synthesis and associated verification such as equivalence checking
  • Background in gate level netlist verification and completeness with respect to power, testability, etc
  • Expertise and in-depth knowledge of industry standard EDA tools