Senior Asic Timing Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +3

This role focuses on ASIC timing analysis and closure for NVIDIA's GPUs, CPUs, LPUs, and SoCs. The engineer will collaborate with cross-functional teams, drive timing convergence, and implement ECOs. Requires BS/MS in Electrical or Computer Engineering with significant experience in Static Timing Analysis (STA), timing constraints, and physical design optimization.

What you'd actually do

  1. Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.
  2. Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
  3. Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams.

Skills

Required

  • BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 3 years’ experience in Timing and STA
  • Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
  • Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
  • Experience in physical design and optimization e.g., synthesis, placement, routing, logic restructuring, etc. to improve timing and power.
  • Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
  • Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.

Nice to have

  • Background in domain specific STA and timing convergence, such as GPUs, CPUs, LPU or SOCs
  • Background in logic synthesis and equivalence checking/FV.
  • Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.
  • Understanding and timing closure of digital logic/macros in AMS designs/IPs.
  • Experience in methodology and/or flow development as well as automation.

What the JD emphasized

  • full-chip/sub-chip Static Timing Analysis (STA) and timing convergence
  • timing constraints generation and management
  • analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
  • physical design and optimization e.g., synthesis, placement, routing, logic restructuring, etc. to improve timing and power
  • industry standard STA and timing convergence tools
  • deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes