Senior Asic Timing Engineer

NVIDIA NVIDIA · Semiconductors · Westford, MA +1

Senior ASIC Timing Design Engineer role focused on physical design and timing of high-frequency and low-power DPUs and SoCs. Responsibilities include analyzing and optimizing design constraints, synthesis parameters, and driving frontend and backend implementation from RTL to GDS2. Requires expertise in Static Timing Analysis (STA), timing constraints, ECO implementation, physical design optimization, logic synthesis, and proficiency in scripting languages.

What you'd actually do

  1. You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, chiplet level, and/or full chip level.
  2. Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.
  3. Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

Skills

Required

  • BS (or equivalent experience) in Electrical or Computer Engineering with 8 years experience or MS with 4+ years experience in Synthesis and Timing
  • Full-chip/sub-chip Static Timing Analysis (STA)
  • Timing constraints generation and management
  • Timing convergence
  • Analysis and fixing of timing paths through ECOs
  • Crosstalk and noise analysis
  • Physical design and optimization (placement, routing, cell sizing, buffering, logic restructuring)
  • Logic synthesis
  • Logical equivalence checking (LEC)
  • Synopsys PrimeTime or Cadence Tempus
  • Python
  • Tcl
  • Make

Nice to have

  • Domain specific STA and timing convergence (CPUs, GPUs or Network processor implementation or SOCs)
  • DFT logic and experience with DFT timing closure
  • Deep sub-micron technology and associated process variations effects
  • Methodology and/or flow development
  • Automation

What the JD emphasized

  • 8 years experience or MS with 4+ years experience in Synthesis and Timing
  • Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence
  • Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
  • Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs
  • Background in logic synthesis and/or logical equivalence checking (LEC)
  • Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus)