Senior Asic Timing Engineer, Dft

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Senior ASIC Timing Engineer, DFT to drive timing analysis and closure for DFT logic on all Nvidia chips. The role involves working with various teams to develop timing constraints, drive convergence, and implement ECOs, while also improving workflows through automation. Requires a BS/MS in Electrical or Computer Engineering with significant experience in Static Timing Analysis (STA) and timing convergence, including expertise in ECOs and timing constraint development.

What you'd actually do

  1. Drive timing analysis and closure for DFT logic on all Nvidia chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full-chip).
  2. Work with PD, DFX, Clocks and other teams to come up with timing closure strategy, develop timing constraints for custom DFT designs, drive timing and power convergence, and implement ECOs.
  3. Continuously improve workflows and designs by introducing more automation, resilience, and standardization.

Skills

Required

  • BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 2+ years’ experience.
  • Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes.
  • Expertise in analysis and fixing of timing paths through ECOs.
  • Expertise in developing timing constraints.
  • In-depth knowledge of industry standard timing convergence tools.

Nice to have

  • Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, iJTAG, etc.
  • Background in domain specific STA and timing convergence, such as Serdes, Processor, IO, SMVA, etc.
  • Experience in methodology and/or workflow development.

What the JD emphasized

  • Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes.
  • Expertise in analysis and fixing of timing paths through ECOs.
  • Expertise in developing timing constraints.