Senior Asic Verification Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Senior ASIC Verification Engineer to verify the design and implementation of SoCs and GPUs, impacting product lines from consumer graphics to self-driving cars and AI. The role involves defining verification scope, developing verification infrastructure, and collaborating with designers. Requires a Bachelors/Masters in EE/CS/CE, 4+ years of verification experience, knowledge of verification techniques (constrained random, scoreboard, functional coverage), SystemVerilog/UVM, and memory subsystem concepts. Experience with AI tools and workflow is a plus.

What you'd actually do

  1. As a Senior Verification Engineer at NVIDIA, you will be responsible for verifying the design, architecture and micro-architecture using advanced verification methodologies
  2. Defining verification scope and driving the development of verification infrastructure, DV strategies and test-planning for memory subsystem units
  3. Collaborate with ASIC designers and architects in feature and micro-architecture discussions.

Skills

Required

  • Bachelors or Masters Degree in Electrical Engineering or Computer Science or Computer Engineering or equivalent experience
  • 4+ years of experience verifying a complex unit from start till tapeout for 1-2 generation of chips.
  • Knowledgeable in verification techniques such as constrained random sequences, scoreboard and functional coverage
  • Experience developing scalable code using Object Oriented Programming principles and proficient in SystemVerilog/UVM.
  • Familiarity with memory subsystem concepts such as memory consistency models, arbitration policies, interface protocols, on-chip interconnect

Nice to have

  • Prior verification experience related to memory subsystem units like caches, xbar/interconnect fabric is a huge plus
  • Strong interpersonal skills
  • Knowledge and hand-on experience with AI tools and workflow.

What the JD emphasized

  • 4+ years of experience verifying a complex unit from start till tapeout for 1-2 generation of chips.
  • Knowledgeable in verification techniques such as constrained random sequences, scoreboard and functional coverage
  • Experience developing scalable code using Object Oriented Programming principles and proficient in SystemVerilog/UVM.