Senior Asic Verification Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +3 · Remote

Senior ASIC Verification Engineer with extensive experience in Design Verification for clocking and reset logic in SOC and GPU ASICs. The role involves owning validation from start to finish, developing scalable solutions, and using industry-standard tools and methodologies.

What you'd actually do

  1. Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
  2. Tackle Sophisticated problems and develop a scalable solution that works across platform.
  3. Hands on industry-standard tools and state of the art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
  4. Partnering closely with our clocks architecture and design team to validate our clocks design.
  5. Coordinate with internal and external teams across time zones.

Skills

Required

  • System Verilog
  • UVM
  • C++
  • Perl
  • Python
  • Logic Design
  • Architecture
  • SV constraint random verification
  • Formal Verification
  • Coverage metrics
  • profiling tools
  • X prop
  • block level and system-level verification
  • Test plans for pre-silicon platforms

Nice to have

  • DFT/IST

What the JD emphasized

  • extensive experience in Design Verification
  • sophisticated verification
  • complex design specifications
  • scalable solution
  • industry-standard tools and state of the art verification methodologies
  • System Verilog, UVM, C++, Perl, Python
  • BS or MS in EE/ECE or equivalent experience
  • 5+ years of relevant industry work experience
  • Expertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.