What you'd actually do

In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models.

You will be responsible for micro-architecture using sophisticated verification methodologies.

As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design.

This role will collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.

Skills

Required

Bachelors or Master’s Degree (or equivalent experience)
3+ years of relevant verification experience
Experience in architecting test bench environments for unit level verification
Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
Prior Design or Verification experience of Coherent high-speed interconnects
Strong background developing TB's from scratch using SV and UVM methodology
C++ programming language experience
scripting ability
expertise in System Verilog
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Strong debugging and analytical skills
Experienced communication and interpersonal skills

Nice to have

Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI
A history of mentoring junior engineers and interns

We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect team! For two decades, we have pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visual computing - the field has grown to encompass video games, movie production, product design, medical diagnosis, and scientific research.

Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from meaningful amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life. As a ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. To learn more about NVIDIA's ultra-fast chip interconnect technology visit: https://www.nvidia.com/en-us/data-center/nvlink-c2c/

What you'll be doing:

In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models.
You will be responsible for micro-architecture using sophisticated verification methodologies.
As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design. This role will collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.

What we need to see:

Bachelors or Master’s Degree (or equivalent experience)
3+ years of relevant verification experience.
Experience in architecting test bench environments for unit level verification.
Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
Prior Design or Verification experience of Coherent high-speed interconnects.
Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful.
Strong background developing TB's from scratch using SV and UVM methodology is desired.
C++ programming language experience, scripting ability and an expertise in System Verilog.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Strong debugging and analytical skills.
Experienced communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until May 3, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.