Senior Asic Verification Engineer, Coherent High Speed Interconnect

NVIDIA NVIDIA · Semiconductors · Hsinchu, Taiwan +1

NVIDIA is seeking a Senior ASIC Verification Engineer to verify the design and implementation of high-speed coherent interconnects for their mobile SoCs and GPUs. The role involves architecting test bench environments, developing verification infrastructure, and collaborating with cross-functional teams. Experience with industry-standard protocols like PCIE, CXL, and CHI is useful, as is expertise in System Verilog and UVM methodology.

What you'd actually do

  1. Responsible for verification of high-speed coherent interconnect design, architecture, golden models, and micro-architecture using sophisticated verification methodologies.
  2. You'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design.
  3. Collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.

Skills

Required

  • Bachelors or Master’s Degree (or equivalent experience)
  • 5+ years of relevant verification experience
  • Experience in architecting test bench environments for unit level verification
  • Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
  • Prior Design or Verification experience of Coherent high-speed interconnects
  • C++ programming language experience
  • Scripting ability
  • Expertise in System Verilog
  • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
  • Strong debugging and analytical skills
  • Experienced communication and interpersonal skills

Nice to have

  • Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI
  • Strong background developing TB's from scratch using SV and UVM methodology
  • A history of mentoring junior engineers and interns

What the JD emphasized

  • 5+ years of relevant verification experience
  • Prior Design or Verification experience of Coherent high-speed interconnects
  • Strong background developing TB's from scratch using SV and UVM methodology is desired
  • C++ programming language experience, scripting ability and an expertise in System Verilog
  • Experienced communication and interpersonal skills are required