Senior Characterization Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Senior Characterization Engineer to test, analyze, and validate Phase-Locked Loop (PLL) circuits after silicon fabrication. The role involves ATE programming, performance optimization, debugging, correlation with simulations, and documentation. Requires deep understanding of PLL architectures and high-speed IO testing, with proficiency in Java, C++, and the Advantest 93000 platform.

What you'd actually do

  1. ATE based Testing & Validation: Perform hands-on, post-silicon characterization of high-speed IOs, single-ended and differential, PLLs and related IP (VCOs, charge pumps, dividers).
  2. Performance Metrics Optimization: Characterize and optimize performance metrics, including TX eye openings, RX jitter tolerance and sensitivity, PLL phase noise, jitter (RMS/peak-to-peak), lock time, frequency range, power supply rejection ratio (PSRR), and power consumption.
  3. Develop ATE programs using the Advantest 93000 platform to automate measurements. design PCB, Operate bench equipment such as waveform analyzers and frequency analyzers when necessary. Analyze large datasets and communicate important findings to the PLL development team.
  4. Work with DFT to ensure accurate test modes are implemented in the chip development phase and help drive ATE vector generation.
  5. Debug & Root Cause Analysis: Identify and fix silicon bugs, PVT (Process, Voltage, Temperature) marginalities, and noise coupling issues.

Skills

Required

  • Bachelor's degree in EE or equivalent experience
  • 12+ years of related experience
  • Deep understanding of PLL architectures (Analog, Digital, Fractional-N, LC, Ring VCOs), feedback loop dynamics, and frequency synthesis
  • Experience in high-speed IO testing, test hardware design and signal integrity
  • Experience with Advantest 9300 platform, high-speed oscilloscopes, spectrum analyzers, and vector network analyzers
  • Strong proficiency in Java and C++ to automate test equipment
  • Experience in analog/mixed-signal validation
  • Ability to work with design, systems, and product engineering teams

What the JD emphasized

  • 12+ years of related experience
  • Deep understanding of PLL architectures
  • Experience in high-speed IO testing
  • Experience with Advantest 9300 platform
  • Strong proficiency in Java and C++