Senior Circuit Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Senior Circuit Design Engineer for Standard Cell Characterization. The role involves working on cutting-edge processor design, standard cell library design and characterization, transistor-level circuit design, modeling, and performance analysis. The engineer will also support and develop tools using Perl/Python, create new simulations for timing/power/noise/OCV evaluations, and collaborate with cross-functional teams on library issues.

What you'd actually do

  1. Work on the cutting edge processor design in deep submicron technologies, and on standard cell library design and characterization. Driving the concepts of the transistor level circuit design, modeling and performance analysis process.
  2. Support and development of tools using Perl/Python.
  3. We will have creative new insights to support existing tools and flows and develop new simulations to perform timing/power/noise/OCV evaluations.
  4. Collaborate with cross function teams with regards to library issues. We will improve on our quality checks on the library work.

Skills

Required

  • MS in Electrical or Computer Engineering or equivalent experience
  • 4+ years of experience
  • strong background in deep submicron process issues
  • Deep understanding of the design, verification and characterization of standard cell libraries
  • Deep understanding on generating timing/power/noise/OCV views of the standard cells, validation of data and QA process
  • Familiar with Liberty models and its application to digital implementation and signoff flows
  • Hands-on experience running SPICE simulation, and capability to adapt to new simulation tools
  • Strong proficiency in scripting language, such as, Perl, Tcl, Make, and automation methods/algorithms
  • excellent team-work, communication and analytical skills
  • able to learn quickly, hard-working, and are results-oriented

Nice to have

  • past standard cell library or IP characterization experience

What the JD emphasized

  • deep submicron technologies
  • standard cell library design and characterization
  • transistor level circuit design
  • modeling and performance analysis
  • timing/power/noise/OCV evaluations
  • quality checks on the library work
  • deep submicron process issues
  • design, verification and characterization of standard cell libraries
  • generating timing/power/noise/OCV views of the standard cells, validation of data and QA process
  • Liberty models
  • SPICE simulation