Senior Compiler Engineer – AI Accelerators (llvm/mlir)

AMD AMD · Semiconductors · Cologne, Germany · Engineering

Senior Compiler Engineer focused on building and optimizing AMD's compiler stack for Neural Processing Units (NPUs) for AI workloads. This role involves frontend and mid-end compiler development, including graph transformations, operator fusion, tiling, memory-layout-aware optimizations, and efficient mapping to accelerator hardware, utilizing LLVM/MLIR.

What you'd actually do

  1. Design, develop, and maintain compiler components targeting AMD AI accelerators, with an emphasis on frontend and mid-end transformations.
  2. Implement and enhance compiler optimizations, including operator fusion, tiling, memory layout transformations, scheduling, and code generation support for AI workloads.
  3. Use C++ and Python to develop compiler passes, test infrastructure, and development tools on top of LLVM/MLIR and related open-source technologies.
  4. Analyze model and benchmark performance, debug compiler issues, and identify efficient mappings of workloads to hardware.
  5. Collaborate with hardware architects, runtime teams, and machine learning framework teams to improve compiler quality, correctness, and performance.

Skills

Required

  • compiler engineering
  • systems software
  • performance-critical software development
  • C++
  • Python
  • compiler fundamentals
  • LLVM
  • MLIR
  • compiler passes
  • software optimizations related to hardware architecture characteristics
  • AI/ML model compilation or deployment
  • compiling for specialized hardware

Nice to have

  • ONNX
  • PyTorch
  • machine learning frameworks
  • graph-level transformations
  • domain-specific intermediate representations (IRs)
  • ML-focused optimizations
  • open-source compiler or AI infrastructure projects
  • Linux-based development environments
  • modern software engineering tools
  • software stacks for AI accelerators or embedded/high-performance computing devices

Other signals

  • compiler development for AI accelerators
  • LLVM/MLIR
  • operator fusion
  • tiling
  • memory-layout-aware optimizations
  • mapping to accelerator hardware