WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. **Together, we advance your career. **
THE ROLE: We are building first-class compilation and code-object tooling for HIP, OpenCL, OpenMP, and the broader ROCm stack. Our compilers, loaders, and post-link tools underpin every HPC application and AI framework that runs on AMD GPUs. We are investing heavily in on-the-fly ISA rewriting and hot-patching infrastructure — inside the Code Object Manager (COMGR) and the AMDGPU backend — that lets us ship hardware fixes, errata workarounds, instrumentation, and performance experiments without recompiling user code. We are looking for a versatile Senior Compiler Engineer who can move fluidly between LLVM MC-level rewriting, ELF/DWARF manipulation, AMDGPU codegen, and the tooling that ties it all together.
This is a multi-year investment area: the rewriting infrastructure starts as an errata-mitigation platform and grows into a long-term foundation for post-link transformation, binary instrumentation, and experimentation across multiple generations of AMD GPU silicon. You will own this codebase as it matures.
THE PERSON: If you are a Compiler Engineer who is equally comfortable reading an LLVM IR pass, disassembling a .text section by hand, reasoning about VGPR liveness across a CFG, and debugging an ELF loader, we would love to talk to you. You enjoy owning problems end-to-end — from hardware erratum to shipped mitigation — and you thrive when the work crosses the traditional compiler/runtime/loader boundaries. You are energized by deep, long-lived systems — the kind of engineer who wants to master a domain across multiple architecture generations, not rotate between short-lived projects.
KEY RESPONSIBILITIES: Design, implement, and maintain the HotSwap ISA rewriting subsystem in COMGR (amd/comgr/src/comgr-hotswap-*) — including ELF patching, DWARF debug-line adjustment, trampoline growth, NOP-sled management, and branch encoding Build and extend LLVM MC-based disassembly, assembly, and re-encoding pipelines used by post-link transformation tools Prototype and evaluate raising-based rewriting pipelines — lifting disassembled AMDGPU machine code into a structured intermediate representation (LLVM MachineIR or a domain-specific in-tree IR) for analysis and transformation, then lowering back to valid code objects Author ISA-specific rewrite policies (e.g., GFX1250 B0-to-A0 style errata mitigations) and generalize them into reusable, ISA-parametric infrastructure Implement and harden CFG construction, backward liveness analysis, and scratch VGPR allocation on raw AMDGPU machine code Adjust ELF section/program headers, AMDGPU notes, kernel descriptors, and code-object metadata safely on malformed or adversarial inputs Contribute to the AMDGPU LLVM backend, Clang driver, and LLD where rewriting needs first-class compiler support Participate in new architecture and silicon bring-ups — owning the compiler/tooling path from bring-up workarounds to long-term codegen quality Analyze, reproduce, and fix issues across the compiler, loader, and runtime boundary; build unit tests, fuzzers, and regressions for each fix Collaborate with ROCm runtime, HSA, and hardware architecture teams spread across geographic locations Represent AMD in open-source communities (e.g., LLVM) and relevant standards bodies (e.g., DWARF Committee) through upstream patches, RFCs, and design reviews
PREFERRED EXPERIENCE: Strong C/C++ programming skills, with a demonstrated ability to write careful, bounds-checked code against untrusted binary input Strong background in compilers and compiler IRs — LLVM IR, MachineIR, or an equivalent production compiler stack Hands-on experience with the LLVM MC layer (MCInst, MCDisassembler, MCCodeEmitter, MCStreamer, TargetRegistry) Experience designing or extending custom in-tree IRs — pass infrastructure, dataflow analyses, SSA construction, dominance, and target-specific lowering — particularly in the context of lifting low-level code into a more analyzable form Exposure to binary lifting / raising — llvm-mctoll, QEMU TCG lifting, RetDec, BAP, angr, or Ghidra P-code — and the practical challenges of reconstructing SSA and control flow from disassembled machine code Working knowledge of ELF, DWARF, and related object-file formats; comfort reading and modifying binaries at the byte level Familiarity with GPU ISAs (AMDGPU / GCN / RDNA / CDNA, or NVIDIA PTX/SASS) — registers, encodings, branch ranges, scheduling constraints Experience with dataflow analyses (liveness, reaching-definitions, dominance) and basic register allocation Understanding of GPU execution models: waves/warps, VGPRs/SGPRs, LDS, kernel descriptors, launch bounds, occupancy Clang/LLVM upstream contribution experience Exposure to the ROCm stack (COMGR, HIP, HSA runtime, hipify) or an equivalent heterogeneous toolchain Background in any of: debug information (DWARF/PDB), binary instrumentation, dynamic binary translation, JIT engines, linker internals, or code-object loaders
ACADEMIC CREDENTIALS: Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent.
This role is not eligible for visa sponsorship.
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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
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This posting is for an existing vacancy.