Senior Cpu Performance Architect

Intel Intel · Semiconductors · Texas, Austin, United States +4

This role focuses on designing and specifying CPU microarchitectures, modeling their performance and power characteristics, and collaborating with cross-functional teams to ensure designs meet stringent requirements. It involves developing end-to-end specifications, evaluating tradeoffs, and debugging performance issues from RTL to silicon.

What you'd actually do

  1. Develops and drives end-to-end CPU microarchitecture specifications for highly optimized, modular, and scalable CPU based on hardware features, requirements, and interoperability of hardware and software throughout the product life cycle.
  2. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel microarchitectures for CPU.
  3. Models CPU performance and power characteristics and analyzes the bottlenecks of current performance features on workloads that reflect CPU future usage.
  4. Collaborates with architects, design, verification, and validation engineers during the execution of the project.
  5. Delivers definition of new microarchitecture and finds mitigations for issues that arise during feature implementation to improve the overall design of CPU and overcome bottlenecks and constraints.

Skills

Required

  • Master's Degree with 10+ years of experience or PhD with 6+ years of experience in high performance, high frequency ARM or x86 CPU performance
  • 8+ years of continuous work within cycle accurate C++ CPU performance simulators
  • Designing high performance CPUs
  • Expertise in CPU domains (Branch Prediction, Fetch/Decode, Rename/Allocation, Reservation Stations/Execution, Memory Subsystem or Prefetchers)
  • Debugging microarchitecture and simulation issues
  • Microarchitecture/RTL/logic development
  • Resolving complex problems, applying analytical and technical skills

Nice to have

  • Background in CPU microarchitecture and experience modeling features in a cycle accurate performance simulator
  • Microarchitecture exploration and identifying new features which provide IPC across the CPU
  • CPU performance related activities from inception to real silicon (pathfinding, definition, correlation with RTL and Post-Si performance debug and tuning)
  • Performance scenarios/use cases and KPI/workloads
  • Advanced skills with Object Oriented Programming (C++/STL) and scripting languages
  • Ability to write assembly and craft tests to evaluate and debug microarchitectural features
  • Ability to read/debug performance issues in RTL

What the JD emphasized

  • continuous work within cycle accurate C++ CPU performance simulators
  • experience in designing high performance CPUs
  • expert in at-least one or multiple domains across the CPU