Senior Custom Circuits Timing Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

This role focuses on custom circuit timing analysis and closure for processor designs, involving standardization and improvement of timing convergence flows, development of timing models, and validation of timing accuracy using simulation tools. The engineer will collaborate with various teams on timing closure strategy, constraints, and ECO implementation.

What you'd actually do

  1. Participate in groundbreaking processor design in deep submicron technologies.
  2. Work as part of a global circuits team alongside custom circuit designers to drive timing analysis and closure of custom circuit macros (digital, semi-custom and mixed-signal analog).
  3. Apply knowledge and experience to standardize and improve timing convergence flows working with methodology teams.
  4. Develop timing models and methodology for innovative and unique custom macro designs at transistor level.
  5. Develop timing models and methodology for standard cell and mixed-signal custom macro designs.

Skills

Required

  • BS (or equivalent experience) in Electrical or Computer Engineering
  • 6+ years of experience for Masters and 8+ years for Bachelors with majority of experience in custom circuit timing analysis/closure.
  • Expertise and in depth knowledge of industry standard transistor level STA tools such as NanoTime and timing convergence tools.
  • Solid experience in timing constraints generation & management, and timing analysis/closure with mixed-signal designs.
  • Basic level understanding of transistor-level circuits and SPICE simulations for correlation to static timing and noise results.
  • Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
  • Knowledge in process variation effect modeling and experience in design convergence taking into account process variations.
  • Familiarity with clocking specs such as jitter, IR drop, crosstalk, etc.
  • Solid understanding of timing models and the usage of .libs in NanoTime as well as PrimeTime

Nice to have

  • Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.
  • Understanding of timing closure of digital logic/macros in AMS designs/IPs.
  • Experience in critical path planning and crafting.
  • Experience in methodology and/or flow development as well as automation.
  • Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes with strong scripting skills for flow automation; experience with TCL, Python is a plus.

What the JD emphasized

  • custom circuit timing analysis/closure
  • timing convergence
  • timing models and methodology
  • timing closure strategy