Senior Design Automation Engineer, Applied AI

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

NVIDIA is seeking an Applied AI Engineer to lead end-to-end solution development for timing and constraint analysis workflows in VLSI/ASIC design. The role involves data generation, model training, orchestration, and building autonomous agents that interact with timing tools. The engineer will develop AI-driven solutions, integrate data sources, implement scalable orchestration, and build interpretable AI pipelines using GNNs, LLMs, and reasoning engines. Experience with Python, PyTorch/TensorFlow, graph/agentic AI frameworks, and EDA tools is required.

What you'd actually do

  1. Architect and develop AI-driven solutions for static timing, constraints quality, and closure prediction.
  2. Integrate heterogeneous data sources — timing reports, constraint graphs, design metadata, silicon correlation — into structured knowledge bases and training pipelines.
  3. Develop autonomous analysis agents that interact with timing tools (e.g., PrimeTime, Nanotime, Tempus) to perform multi-corner, multi-mode optimization and constraint debugging.
  4. Implement scalable orchestration across Flow-Server and Digital Engineer platforms, enabling AI-in-loop decision-making for sign-off readiness.
  5. Collaborate with methodology and sign-off teams to validate models on live projects, improving coverage, predictability, and engineering productivity.

Skills

Required

  • BS (or equivalent experience) in Electrical or Computer Engineering with 12+ years of experience in AI/ML solution development
  • Strong background in VLSI/ASIC design
  • Proficiency in Python, PyTorch/TensorFlow
  • Experience developing data pipelines, knowledge graphs, or process models for structured engineering data
  • Working knowledge of timing tools (PrimeTime, Nanotime, Tempus) and scripting integration with EDA environments

Nice to have

  • graph or agentic AI frameworks (e.g., LangGraph, LangChain, Ray, NetworkX)
  • Experience with AI orchestration frameworks, reasoning based on prompts, and multi-agent automation
  • Experience with constraint validation, false-path detection, and timing-exception modeling
  • Prior exposure to AI in physical design automation, Silicon/process modeling, or EDA flow automation
  • Contributions to open-source AI or flow automation projects
  • Publications or patents in AI for design automation or semiconductor engineering

What the JD emphasized

  • deep understanding of timing, constraints, STA, or sign-off workflows
  • Experience with AI orchestration frameworks, reasoning based on prompts, and multi-agent automation is highly desirable.

Other signals

  • AI-driven solutions for static timing, constraints quality, and closure prediction
  • Develop autonomous analysis agents that interact with timing tools
  • Implement scalable orchestration across Flow-Server and Digital Engineer platforms
  • Build interpretable AI pipelines using graph neural networks, large language models, and process-aware reasoning engines