Senior Design Engineer – AI Soc Development

Intel Intel · Semiconductors · California, Folsom, United States +3

Senior Design Engineer focused on developing logic design, RTL coding, and simulation for AI SoC development, integrating IP blocks, defining architecture, and optimizing for power, performance, and timing. The role involves collaboration with verification teams, driving silicon bring-up, and mentoring junior engineers.

What you'd actually do

  1. Lead evaluation of architectural trade-offs considering features, performance targets, power constraints, and system limitations
  2. Define and document micro-architecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver fully verified, synthesis- and timing-clean designs
  3. Collaborate closely with verification teams to ensure comprehensive coverage and robust validation of all design aspects
  4. Develop and maintain timing constraints for IP blocks; provide guidance and support to physical design teams for synthesis, timing closure, and formal equivalence checks
  5. Drive silicon bring-up and post-silicon validation, including debug and performance analysis

Skills

Required

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
  • 7+ years of experience in RTL design and implementation for ASIC/SoC development

Nice to have

  • Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure
  • Hands-on experience with SoC system integration and multicore CPU subsystem design
  • Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
  • Expertise in high-speed and low-power design techniques
  • Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization
  • Familiarity with industry standard EDA tools, including simulators (VCS, Questa, Xcelium), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II)
  • Ability to thrive in a dynamic environment with evolving requirements
  • Strong communication skills
  • Collaborative mindset
  • Leadership qualities

What the JD emphasized

  • 7+ years of experience in RTL design and implementation for ASIC/SoC development