Senior Design Engineer - Chassis Component Ip

Intel Intel · Semiconductors · Bangalore, India

Senior Design Engineer for Intel Chassis Group, focusing on logic design of component IPs for SoC chassis. Responsibilities include designing protocol conversion bridges, debug/trace components, and clock/power controls, translating standard protocols to custom transport protocols while managing QoS, Access Control, Flow Control, RAS, and Error Handling.

What you'd actually do

  1. logic design of component IPs which can be used to build an SoC chassis
  2. design of protocol conversion bridges for control and data planes that translate standard protocols such as AMBA/CXL to a custom transport protocol developed for the chassis, while also accounting for QoS, Access Control, Flow Control, RAS, Error Handling and Hashing
  3. good understanding of debug and trace networks
  4. designing clock/power controls

Skills

Required

  • Verilog/System Verilog
  • Lint/CDC/RDC
  • AMBA (CHI, AXI, AHB, APB)
  • Coresight
  • PCIe/CXL protocols
  • coherency concepts
  • DVFS
  • UPF
  • power, performance and area trade-offs
  • physical design
  • timing limitations
  • leading edge TSMC and or Intel nodes
  • MMU design
  • Jinja-based templating

Nice to have

  • design of protocol conversion bridges for control and data planes
  • debug and trace networks
  • designing clock/power controls

What the JD emphasized

  • 8+ years of experience in state-of-the-art SOC and/or IP design
  • 5+ years' experience in design of protocol conversion bridges for AMBA/PCIe/CXL protocols with QoS, flow control, access control, hashing and error handling features, and/or debug trace networks