Senior Design Engineer, Coherent High Speed Interconnect

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior Design Engineer role focused on the architecture and design of high-speed coherent interconnects (NVLINK-C2C) for NVIDIA's mobile SoCs and GPUs. This involves collaboration with various teams to deliver a class-leading interconnect solution that enables chiplet-based integrated products.

What you'd actually do

  1. You will be working on architecture and design of our state-of-the-art high speed coherent interconnects (NVLINK-C2C) for our mobile SoCs and GPUs.
  2. Collaborate with architects, external partners, software engineers, and circuit designers to deliver a class leading high speed coherent interconnect.
  3. The NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon.
  4. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
  5. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

Skills

Required

  • Electrical Engineering or Computer Engineer or related degree
  • 6+ years of relevant design experience
  • Knowledge of industry standard interconnect protocols (PCIE, CXL, AXI, CHI)
  • Understanding of Link layer stacks (Data link layer and Physical layer)
  • Experience with physical layer of interconnects (Memory, PCIE, SerDes)
  • Experience in architecture, RTL design, performance analysis and power optimization
  • Verilog or System Verilog
  • Communication skills
  • Interpersonal skills

Nice to have

  • advanced degrees (MS, PhD)
  • mentoring junior engineers and interns

What the JD emphasized

  • BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required
  • 6+ years or relevant design experience
  • Knowledge of industry standard interconnect protocols like PCIE, CXL, AXI, CHI will be useful.
  • Understanding or experience with Link layer stacks including Data link layer and Physical layer
  • Experience with physical layer of interconnects such as Memory (DDR, LPDDR etc..) , PCIE , SerDes
  • Experience and knowledge in architecture, RTL design, performance analysis and power optimization.
  • Strong working knowledge of Verilog or System Verilog.
  • Good communication skills and interpersonal skills are required.