Senior Design-for-test Engineer, Atpg

NVIDIA NVIDIA · Semiconductors · Tel Aviv, Israel +1

NVIDIA is seeking a Senior Design-for-Test Engineer to join their ATPG team in Israel. The role involves working on groundbreaking innovations in DFT architecture, verification, and post-silicon validation for sophisticated semiconductor chips. Responsibilities include managing state-of-the-art Design for Test/ATPG flows, end-to-end ATPG ownership, and inventing automation flows for short test times. Requires 5+ years of DFT/ATPG experience, strong scripting skills, and a BSc in Electrical Engineering or Computer Engineering.

What you'd actually do

  1. You will be in charge of state of the art Design for Test/ATPG flows and implementation
  2. Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.
  3. Inventing and maintaining automation flows that provide the short test time to production

Skills

Required

  • DFT/ATPG experience
  • DFT ASIC Design
  • ATPG tools
  • scripting languages
  • BSc. in Electrical Engineering or Computer engineering

Nice to have

  • scan
  • BIST
  • on-chip scan compression
  • fault models
  • fault simulation
  • Mentor TestKompress ATPG tool
  • retargeting flow
  • TCL
  • PRL
  • Phyton
  • Unix shell scripts
  • ATE
  • Silicon bring-up

What the JD emphasized

  • 5+ years of hands on DFT/ATPG experience knowledge & technical experience in DFT ASIC Design and in ATPG tools