Senior Design Verification Engineer

Microsoft Microsoft · Big Tech · Austin, TX +4 · Silicon Engineering

This role is for a Senior Design Verification Engineer in the semiconductor industry, focusing on the design and verification of computer chips for Microsoft's cloud infrastructure. The role involves developing verification environments, running simulations, and applying AI solutions to improve verification efficiency. While AI tools are mentioned, the core function is hardware verification, not AI model development.

What you'd actually do

  1. Own or lead verification of complex flows at Fabric Interconnect or at block level
  2. Learn about the design and interact with partner teams to define verification strategies and test plans
  3. Develop UVM-based verification environments and run and debug simulations to drive quality
  4. Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
  5. Innovate to improve verification efficiency through methodologies or tools

Skills

Required

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Nice to have

  • 5+ years of pre-silicon subsystem or IP verification experience.
  • Demonstrated experience in verifying designs that utilize Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols
  • Demonstrated experience in one or more of the following: fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges
  • Experience driving IP verification for a full product cycles from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff
  • Demonstrated hands-on technical leadership such as creating bottom’s up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems
  • Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking
  • Aptitude for writing scripts/software with industry standard languages like Python
  • Experience applying generative AI to day-to-day tasks

What the JD emphasized

  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • This role will require access to information that is controlled for export under export control regulations