Senior Design Verification Engineer

AMD AMD · Semiconductors · Hyderabad, India · Engineering

Senior Design Verification Engineer role focused on planning, building, and executing verification of wired networking IP features. Responsibilities include collaborating with architects and engineers, building test plans, writing and debugging directed and random verification tests, and reviewing coverage metrics. Requires proficiency in IP level ASIC verification, UVM, and SystemVerilog.

What you'd actually do

  1. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  2. Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  3. Estimate the time required to write the new feature tests and any required changes to the test environment
  4. Build the directed and random verification tests
  5. Debug test failures to determine the root cause and work with RTL and firmware engineers to resolve design defects and correct any test issues
  6. Review functional and code coverage metrics and modify or add tests or constrain random tests to meet the coverage requirements

Skills

Required

  • IP level ASIC verification
  • Debugging RTL code using simulation tools
  • UVM concepts
  • SystemVerilog language
  • UVM testbenches
  • Linux environment
  • Windows environment
  • Scripting language experience: Perl, Python, Makefile, shell

Nice to have

  • Developing UVM-based verification frameworks and testbenches, processes, and flows
  • Automating workflows in a distributed compute environment
  • Simulation profile, efficiency improvement, acceleration, and formal verification
  • Leadership or mentorship
  • Networking protocols such as Ethernet, UAL, LLR, and CBFC
  • AI tools