Senior Design Verification Engineer- Mixed Signal Ip

Intel Intel · Semiconductors · California, Folsom, United States +1

Senior Design Verification Engineer for Mixed Signal IP at Intel, focusing on functional verification of mixed signal logic components, developing IP verification plans, test benches, and verification environments. Responsibilities include executing verification plans, running system simulation models, debugging issues in the presilicon environment, and collaborating with digital and analog architects, RTL developers, and physical design teams. Requires BS/MS/PhD in Engineering with significant experience in design verification, System Verilog, and OVM/UVM.

What you'd actually do

  1. Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
  2. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications.
  3. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
  4. Replicates, root causes, and debugs issues in the presilicon environment.
  5. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.

Skills

Required

  • BS degree in Computer Engineering/Computer Science/Electrical Engineering or related field with 8+ years of relevant industry experience in Design verification, System Verilog and OVM/UVM or MS degree in Computer Engineering/Computer Science/Electrical Engineering or related field with 6 + years of relevant industry experience or a PhD in Computer Engineering/Computer Science/Electrical Engineering or related field with & 4+ years
  • Design verification
  • System Verilog
  • OVM/UVM

Nice to have

  • validation flow right from test plan creation to verification closure
  • waveform debug
  • functional coverage
  • code coverage
  • VCS NLP and non-NLP simulations and GLS
  • DDRPHY validation with good hold on DFI/DDR/LPDDR protocols
  • scripting skills in Python/Perl
  • Formal Property Verification
  • Git/Perforce/CVS version control

What the JD emphasized

  • relevant industry experience
  • relevant industry experience
  • relevant industry experience
  • Design verification
  • System Verilog
  • OVM/UVM
  • validation flow right from test plan creation to verification closure
  • waveform debug
  • functional coverage
  • code coverage
  • VCS NLP and non-NLP simulations and GLS
  • DDRPHY validation
  • DFI/DDR/LPDDR protocols
  • scripting skills in Python/Perl
  • Formal Property Verification
  • Git/Perforce/CVS version control