Senior Design Verification Engineer - Pcie

NVIDIA NVIDIA · Semiconductors · Taipei, Taiwan +1

Senior Design Verification Engineer for PCI Express controllers used in GPUs, SOCs, and DPUs. Requires expertise in verification methodologies like UVM and Specman/e, and knowledge of industry standard protocols.

What you'd actually do

  1. Verification of the ASIC design, architecture, and micro-architecture of PCIE controllers for multiple product generations for GPUs, SOCs & DPUsat IP/sub-system levels using standard verification methodologies such as UVM and Specman/e.
  2. Develop UVM or Specman/e based testbench components reusable across verification methodologies and integrate those across verification environments.
  3. Build or improve reusable testbench components including constraints, stimulus, monitors, checkers and scoreboards following coverage based verification methodology.
  4. Understand complex testbench and its verification scope with respect to the design specification and implementation, define new verification scope as per design or verification methodology requirements, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
  5. Collaborate with multiple verification teams, architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Skills

Required

  • SystemVerilog
  • UVM
  • Specman/e
  • PCI Express
  • CXL
  • UCIe
  • USB
  • SATA
  • constrained random verification
  • reusable testbench architecture

Nice to have

  • UVM
  • Specman/e
  • PCIE protocol - Gen3 and above
  • debugging
  • analytical skills
  • interpersonal skills

What the JD emphasized

  • Verification of the ASIC design, architecture, and micro-architecture of PCIE controllers for multiple product generations for GPUs, SOCs & DPUsat IP/sub-system levels using standard verification methodologies such as UVM and Specman/e.
  • Develop UVM or Specman/e based testbench components reusable across verification methodologies and integrate those across verification environments.
  • Build or improve reusable testbench components including constraints, stimulus, monitors, checkers and scoreboards following coverage based verification methodology.
  • Understand complex testbench and its verification scope with respect to the design specification and implementation, define new verification scope as per design or verification methodology requirements, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.